AMD: Optimizations for shader splits in chiplet design

AMD already wants to take a similar step with RDNA 3 as in the CPU market and introduce a chiplet design that should reduce waste compared to large monolithic dies. In addition, the hardware manufacturer has submitted several patent applications in the USA, which are intended to protect the basic technologies. However, the 54 applications in total also deal with technology that lies further in the future, so that a clear differentiation is currently not possible.

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A particular challenge for the new architecture is the utilization of the two chiplets when rendering. While a monolithic chip can also use a large number of compute units with the help of its scheduler, the main limitation in a chiplet design is the connections between the chiplets. However, since no development has been made here so far, the software is up to date, so to speak, when the first dual-core CPUs were released. Two-level binning is supposed to be a solution to this problem.

This changes the rasterizer pipeline so that it divides a scene into two levels instead of blocks of pixels. This division of the geometry is called vertex shading and ensures that the first chiplet only has to do minimal preparatory work until a coarse binning is completed, while the coarse bins can then be processed by one chiplet at a time.

Finally, the vertex shading is finished and post-processing effects can be edited. The division and communication of such processes is done through the primary chiplet, while the other chiplets operate on assignment only. AMD has patented a concept for dynamic distribution that is intended to ensure maximum efficiency for even utilization and sensible distribution of the load.

Source: computer base & FPO