Nvidia Grace and Hopper: First details of the hot chip presentation released

The Hot Chips semiconductor trade fair takes place every year in August, where exciting details about current or upcoming products from AMD, Intel and Nvidia are often published. This year is no exception: In preparation for the trade fair, Nvidia has released the first details on the Grace CPU and the Hopper GPU, both of which are being developed for use in supercomputers.

Manufacturing, performance and interconnect details

In the future, Nvidia wants to market Grace and Hopper as “superchips”: The Grace superchip is to combine two Grace CPUs, each with 72 ARM cores, on one motherboard, while the Hopper superchip is a Grace CPU and a Hopper GPU united. As Nvidia has now confirmed, both chips will use TSMC’s N4 manufacturing, which is an improved 5nm process.

The internal communication of the Grace CPU relies on Nvidia’s Scalable Coherency Fabric.

Source: Nvidia (via Tom’s hardware)



According to Nvidia, the communication between the individual ARM Neoverse cores in the Grace GPU should take place via the Scalable Coherency Fabric (SCF): A mesh network that offers 3.2 TB/s bandwidth and the individual cores, the memory and connects the I/O circuits. The basis for the technology should be the CMN-700 mesh network developed by ARM for the Neoverse cores, which Nvidia adapted for the specific CPU design.

Grace is supposed to communicate externally with NVLink: This is how data is exchanged with the second Grace chip or a hopper chip. In addition, Grace should also have standard connections: According to Nvidia, 68 PCI Express 5.0 lanes and 16 dual-channel connections for LPDDR5X are planned per CPU. In total, a maximum of 512 GB of memory can be connected to the CPU, which is processed at up to 546 GB/s. Nvidia justifies the use of LPDDR5X instead of HBM2e with advantages in terms of costs and storage capacity.

The Grace CPU is said to offer 12 NVLink lanes and 68 PCI Express 5.0 lanes.

Source: Nvidia (via Tom’s hardware)

Nvidia also wants to enable direct memory access between different clusters.

Source: Nvidia (via Tom’s hardware)



Despite the different memory technologies, a hopper GPU with HBM2e should also be able to access the memory of a Grace CPU – even if it is housed on a different mainboard. Communication takes place again via NVLink. The interface used by Nvidia should be able to work with a maximum of 900 GB/s and five times the energy efficiency of PCI Express 5.0. When accessing a single chip, the bandwidth of the LPDDR5X memory would therefore be limiting.

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Finally, Nvidia also has performance values ​​ready. According to the company, a single Grace chip should achieve 370 points in the “SpecIntRate 2017” benchmark, while two of the chips should achieve exactly double the performance with 740 points. For comparison: AMD’s current Epyc Milan flagship achieves 382 to 424 points per CPU.

Of course, it is not just the raw performance that is decisive for success, but also the price and, in particular, the efficiency. It should also be noted that the Grace performance values ​​are only estimates due to the lack of ready-made hardware. The CPU is not expected to hit the market until 2023.

It remains to be seen whether Nvidia has already anticipated all the new information from the hot chips fair with the details presented here. On Monday, the company will be talking about the Hopper GPU there, and on Tuesday it’s supposed to be about the Grace CPU. AMD and Nvidia will also talk about their upcoming HPC products at the show.

Source: Tom’s hardware