PCGH Readers Ask: What to expect from Intel’s Tile CPUs in terms of efficiency?

Some interesting reader questions have arisen from the discussion about Intel’s CPU plans for 2023 and 2024. PCGH has answered one or the other question, at this point we want to present one of the answered questions to a broader public.

The reader question from Rollora:

“As far as I can remember, AMD’s chiplet approach has efficiency disadvantages compared to monolithic chips in low-load scenarios and when idling. Is this also to be expected with Intel’s “Tile” CPUs?”

The answer from Torsten Vogel (mainboards department):

“Almost certainly, but probably to a lesser extent. Intel speaks of “quasi monolithic silicon” for Sapphire Rapids; the inter-chip connects should not be at the expense of performance. But obviously you can’t just run the mesh via EMIB, but needs a modified transmit-receive system. However, additional units with transmission power naturally consume additional power, and that takes revenge, especially at medium load or when a few cores are running at full power. So whenever the computing units themselves only consume little power, man but cannot downclock the interconnects because full data access must be available.

With AMD’s Zen 2 Epycs, just half of the TDP budget was available to the cores even under full load, the rest was eaten up by the uncore area (including octa-channel RAM controller) from a load of 50 percent (source). With similar considerations in mind, Intel is now offering an “Optimized Power Mode” for Sapphire Rapids, which costs an average of 5 percent computing power with changing loads, but is also said to save up to 20 percent power consumption by aggressively downclocking the fabric instead always keep everything ready under full steam.

All non-monolithic designs, including Intel’s tile processors, have to face this fundamental loss of efficiency compared to a monolith with otherwise identical technology. Just as with AMD’s change from monolithic Zen(+) to chiplet Zen 2 CPUs, parallel efficiency improvements through new architectures and manufacturing processes can (hopefully!) overcompensate for this disadvantage, resulting in better overall efficiency than the previous generation – only just not quite as good as would be conceivable with a potentially more expensive single-chip approach.”

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